This invention relates to a high speed memory circuit having a function which can shift by n addresses a data storage address simultaneously with a read-out operation of data held by a memory circuit, and also to a method of controlling the high speed memory circuit.
In order to accomplish a high speed operation of an integrated circuit, a method has been practised recently which divides the circuit into several functional blocks and effects data processing using a pipeline technique to shorten the through-put of the circuit as a whole. However, the through-put time is determined by a circuit which requires the longest processing time among these functional blocks.
If a memory circuit has a read cycle and a write cycle (the processing time of both of which is hereby assumed to be T) in a single operation cycle, the operation cycle of the memory circuit is 2T, but if either one of the read operation and the write operation is permitted in one operation cycle of the memory, the operation cycle of the memory circuit becomes the time T, so that the through-put time of the integrated circuit as a whole can be shortened, as is well known in the art.
In various operations for signal processing, however, an operation which reads out the data from the memory and an operation which shifts the address for storing the read-out data from an address a.sub.o to a.sub.o+n (a so-called "read-modify-write operation") is frequently performed. In such a case, the 2T time is necessary for the read-modify-write operation for both of the two systems described above, and the processing speed drops remarkably.